1. Field of the Invention
This invention relates to polishing and grinding technique for planarization of the substrate surface and a semiconductor device manufacturing apparatus that uses such planarization technique, and more particularly relates to a manufacturing method of a semiconductor device for polishing or grinding a thin film formed on a semiconductor substrate and a manufacturing apparatus of a semiconductor device.
2. Description of the Prior Art
In recent years, planarization technique for shallow trench isolation, for forming of a tungsten (W) plug that is served for transmitting a signal from a transistor element to a wiring layer, and for forming of a wiring layer has been important. The polishing technique called as chemical mechanical polishing is typically employed in the field of planarization technique.
In the field of planarization technique, copper has been used popularly as the wiring material. The damascene method has been employed mainly as the planarization technique. For example, Japanese Patent Laid-open No. Hei2-278822 and Japanese Patent Laid-open No. Hei8-83780 disclose such polishing technique.
Copper wiring material is advantageous in that the durability is improved and the resistance value is reduced in comparison with the conventional aluminum wiring material, but on the other hand, disadvantageous in that the insulation is poor due to conductive copper ions that diffuse into the oxide film. The poor insulation should be avoided. In damascene method, a barrier metal film 14 formed on the interface between an oxide film 13 and the copper wiring material 15 prevents copper ions from being diffused as shown in FIG. 11A. In the damascene method, the barrier metal film 14 allows the copper 15 to be filled in the trench through the process including A step to C step shown in FIG. 11A to FIG. 11C.
For the copper wiring forming process in the damascene method, the control of the removal rate of the copper 15 and barrier metal film 14 is important. The term “removal rate” means the removed quantity of a target material per unit time. Generally, because the removal rate of a barrier metal film (Ta, or TaN is used usually) is slower than that of copper, the copper is removed excessively when the process of the step A to step C is carried out all at once. To avoid the problem, in the usual slurry working, a plurality of slurries including a slurry that polishes copper at high removal rate, a slurry that polishes a barrier metal film at high removal rate and polishes copper at low removal rate, and a slurry that polishes copper, barrier metal film, and oxide film at the same removal rate are used separately. In the actual CMP process, the step A shown in FIG. 11 is carried out by use of the slurry that polishes copper at high removal rate, and then the next step is carried out by use of the slurry that polishes a barrier metal film with changing a polishing platen. In some cases, to improve the planarity and reduce the scratch, the additional CMP is carried out by use of the slurry that polishes copper, barrier metal film, and oxide film at the same removal rate.
Otherwise, another conventional technique in which fixed abrasive 12 is used for planarization of copper has been employed. A sheet on which alumina abrasive is fixed with resin is used. This technique is characterized in that slurry containing free abrasive 16 is not required. However, this technique also still requires the second and third step CMP as in the above-mentioned technique for removing the barrier metal film 14. This technique is described in “2000 Chemical Mechanical Planarization for ULSI Multilevel Interconnection Conference proceedings pp. 58 to 65.
Furthermore, another conventional technique in which fixed abrasive is used is described in U.S. Pat. No. 5,972,792 exemplarily. In this technique, planarization is carried out while pH of the polishing liquid 8 is controlled to prevent a target material from being etched. This technique also belongs to the multi-step planarization method in which polishing method is changed for each target material by use of fixed abrasive.
Furthermore, Japanese Patent Laid-open No. Hei10-329031 and Japanese Patent Laid-open No. 2000-233375 disclose a polishing technique in which a grindstone containing pores is used. Such grindstone is manufactured by use of, for example, thermosetting resin that is self-foamable or rendered foamable with foaming agent. Furthermore, the above-mentioned Japanese Patent Laid-open No. 2000-233375 discloses a polishing technique in which a grindstone having arranged small segmented grindstones.
The above-mentioned damascene methods for planarization by means of CMP is involved in some problems. One of them is that separate two or more steps of CMP are necessary for CMP of copper and barrier metal film because Ta or TaN, which is used for the barrier metal film, is harder than copper as described hereinbefore, and the multi-step CMP results in increased cost, low through-put, and increased environmental load due to increased waste slurry.
Furthermore, the softness of a polishing pad results in dishing or erosion as shown in FIG. 11A to FIG. 11C and FIG. 5, which means the concave forming on the wiring surface, and the dishing or erosion further resultantly causes increased dispersion of wiring resistance value. Particularly the above-mentioned problem is serious for the logic device called as system LSI having multi-layer wiring structure as shown in FIG. 8. In detail, if the planarity of the bottom layer is poor as shown in FIG. 7, the planarization is more insufficient than expected for CMP, and the short-circuit or disconnection due to insufficient polishing is apt to occur. The above-mentioned problems have remained unsolved. The detail of the problems is described in “Next Generation ULSI Multi-Layer Wiring New Material/Process Technology” pp. 242 to 246 by Technical Information Association.
It is the first object of the present invention to provide a method for manufacturing a semiconductor device with less dishing or erosion.
It is the second object of the present invention to provide an apparatus for manufacturing a semiconductor device with less dishing or erosion.
It is the third object of the present invention to provide a method for manufacturing a semiconductor device and an apparatus for manufacturing a semiconductor device through one step process instead of conventional process comprising two or more steps.